1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly, to methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal, and related structure.
2. Related Art
Semiconductor devices include a plurality of circuits which form an integrated circuit (IC) including chips (e.g., chip back end of line, or “BEOL”), thin film packages and printed circuit boards. Integrated circuits can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of integrated circuits increase. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. “Damascene” is a process in which interconnect patterns are first lithographically defined in the layer of dielectric then metal is deposited to fill resulting trenches and then excess metal is removed by means of chemical-mechanical polishing (CMP) (planarization). “Dual damascene” is a similar process in which two interlayer dielectric patterning steps and one CMP step create a pattern which would require two patterning steps and two metal CMP steps when using a conventional damascene process. Within the interconnection structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip include at least about 2 to 8 wiring levels fabricated at a minimum lithographic feature size designated about 1×(referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a width equal to about 2× and/or about 4× the minimum width of the thinwires (referred to as “fatwires”). In one class of structures, the thinwires are formed in a low dielectric constant (k) organosilicate (SiCOH) inter-level dielectric (ILD) layer, and the fatwires are made in a silicon dioxide (SiO2) ILD having a dielectric constant of about 4.
One of the many challenges associated with the fabrication of the thin and fatwires for 65 nm and beyond complementary metal-oxide semiconductor (CMOS) technologies is the issue of ash (strip) induced modification of the ultra low-k (ULK) interlayer dielectric (ILD) material during single/dual damascene processing. For specific integration schemes, once the trench or via structure is defined during the damascene process flow, the resist (or other organic materials) must be removed. This resist removal is typically done using dry plasma processing conditions on the dual frequency capacitive (DFC) etch platform on which the damascene processing occurred (i.e., using in situ ashing) or on some other plasma etch/ash tool (i.e., ex situ ashing). However, the interconnected nature of the pore structure within these so-called ULK materials implies ready susceptibility to carbon removal and consequent moisture uptake upon exposure to various photoresist (organic material) removal plasmas, which rapidly destroys the ULK properties of the dielectric film. As such, there is significant demand for a suitable ash process for these specific integration schemes that employ ULK ILD technology which facilitates minimal/negligible ULK film modification. One such candidate is an ex situ downstream hydrogen-based process conducted at elevated temperature and pressure on a platform distinct from the DFC platform. In general, the use of a downstream plasma eliminates the possibility of ion impact to the ILD sidewalls and further minimizes the possibility of film modification. Thus, other downstream plasma chemistries may also be appropriate for enabling reduced ULK ILD film modification.
There are, however, a few issues with such an approach. First, the use of such a high flow and high pressure-based process (e.g., liters per minute and 100s of mTorr) facilitates potential removal of residual fluorine physisorbed onto the wafer surface post single/dual damascene processing. This physisorbed fluorine is present on the wafer surface after damascene processing (trench or via creation) as fluorine-based chemistries are necessary for etching these porous organosilicate glass (OSG) films on the DFC platform. During the downstream plasma ash process, however, physisorbed fluorine is liberated (by high gaseous flow˜liters/min) from the wafer surface, which entices subsequent isotropic etching of the ULK film and other materials in the stack. This can be a particularly pernicious occurrence not only for the ULK film but also for the ILD adhesion promoter. Such ULK builds typically employ an inorganic adhesion promoter (15–30 nm thick layer) to improve the cohesive strength between the ILD and barrier layer films. If this adhesion promoter is consumed or partially consumed during the downstream plasma ash process, the integrity/consistency of the interconnect structure is inevitably compromised.
A further drawback of downstream ash options is the inability to remove chemisorbed fluorine present in the field area chemisorbed to the resist or other organic material. Since the etch chemistries utilized to define the damascene structures must be fluorine-based, post processing, the resist or organic planarizing layer that served as a pattern transfer layer typically has various carbon-flouride (CFx) species chemisorbed onto its surface. The negligible presence of ions in a downstream plasma ash process (which is one of the advantages of the process from an ILD modification viewpoint) reduces the ability of the downstream plasma ash process to remove such chemisorbed fluorine-based residue. As a result, the field area of the wafer surface can be typically covered with such chemisorbed fluorine-based species after damascene (conducted on the DFC etcher) and downstream ash processing (conducted on the downstream asher). This residual chemisorbed fluorine is oftentimes removed post ash processing via some aqueous or non-aqueous means. Such wet processing, however, can potentially impact the dielectric properties of the ULK film.
Presently, there are approaches for performing cleans for miscellaneous applications that employ a nitrogen and/or hydrogen containing chemistry. However, these processes are inadequate for removing chemisorbed or physisorbed fluorine-based residues because they all employ ion current (˜ion density×ion energy) conditions that would induce significant ULK film modification and/or plasma induced charging damage.
In view of the foregoing, there is a need in the art for a method that eliminates physisorbed and chemisorbed fluorine from a wafer surface associated with non-damaging downstream plasma photoresist removal of ULK interconnect builds.